ARM Demonstrates Complete Solution for SOC Backplane Design with Fabric and Verification IP
ARM will demonstrate its innovative range of complementary AMBA® protocol-based fabric and verification IP solutions for the design and analysis of c...
Posts tagged as lane
Backplane tutorial: RapidIO, PCIe and Ethernet
RapidIO, PCIe, and Ethernet each offer unique benefits. We explain how each technology works, and examine its strengths and weaknesses. We also show w...
MIPI D-Phy Bi-directional Master/Slave Dual Lane in TSMC 40LP from MIPS Technologies
MIPI D-Phy Bi-directional Master/Slave Dual Lane in TSMC 40LP from MIPS Technologies...
4-lane Dual-Mode MIPI CSI2 / SMIA CCP2 Serial Video Receiver from VLSI Plus
4-lane Dual-Mode MIPI CSI2 / SMIA CCP2 Serial Video Receiver from VLSI Plus...
4-lane Dual-Mode MIPI CSI2 / SMIA CCP2 Serial Video Receiver from VLSI Plus
4-lane Dual-Mode MIPI CSI2 / SMIA CCP2 Serial Video Receiver from VLSI Plus...
Blue Wonder Communications to Develop LTE Baseband IP Using Multiple Optimized Tensilica Dataplane Processors
Tensilica today announced that Blue Wonder Communications has licensed Tensilica's Xtensa dataplane processors (DPUs) for an LTE (Long-Term Evolution...
Micrium broadens its support for Tensilica into dataplane architectures
Micrium uC/OS-II RTOS to be ported to Tensilica's Xtensa architecture. ...
Micrium broadens its support for Tensilica into dataplane architectures
Micrium uC/OS-II RTOS to be ported to Tensilica's Xtensa architecture. ...
Achieve Higher Backplane Density
Equipment designers, particularly those involved with communications and high-end data, face the constant challenges of increasing data rates and grea...
Dataplane Processing Unit More Flexible Than DSP
Baseband communications dataplane processing is one of the most demanding environments around. Tensilica’s ConnX Baseband Engine is designed to...