New Release of the OVM Takes Verification to the Next Level
The new release extends the proven sequential stimulus mechanism in the OVM with transaction-level modeling (TLM) interfaces to improve the modularity...
Posts tagged as level
Agilent Technologies' New Electronic System-Level EDA Platform Helps Algorithm Developers, System Architects Cut Design Time in Half
The new platform cuts physical layer (PHY) design time in half for high-performance communications algorithms and system architectures, for both wirel...
Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System
Aldec, Inc. announced today that Thales has decided to deploy the DO-254/ED-80 CTS(Compliance Tool Set) from Aldec. The DO-254/ED-80 CTS is an In-Hard...
Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters to Boost Acceleration and Emulation Performance
The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth...
Trace Based Approach for Unit Level Debug and Verification of C/C++ IP Models
This paper discusses a Standalone verification framework that is independent of any specific flow but still allows reuse of Design Verification & ...
Lattice Delivers Flexible, Programmable 40 Gbps Serdes Framer Interface, Level 5 (SFI5) IP Core Solution
Lattice today announced the availability of the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core in the LatticeSC/M FPG...
Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and Xilinx FPGAs
Cadence today announced the integration of FPGA-synthesis for Altera and Xilinx FPGAs with the Cadence® C-to-Silicon Compiler, its flagship electroni...
Mentor Graphics Announces Scalable TLM-2.0 Design Flow Using Vista and Catapult C Synthesis Electronic System Level (ESL) Design Tools
Mentor Graphics today announced a new Scalable Design Methodology based on a layered transaction level model (TLM) that allows a single model to be ta...
Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite
Mentor Graphics today announced completion of the acquisition of the C synthesis assets of Agility Design Solutions Inc. These tools were formerly own...
How High-Level Synthesis Can Raise the Efficiency of Design Reuse
In this paper we present a design methodology based on high-level synthesis that allows retargeting functional IPs in the form of C++ programs to tech...