The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth and Depth...
eInfochips today announced the availability of JEDEC (JESD79-2D) compliant DDR2 SDRAM verification IP and European DVB, IEEE 802.16, IESS, ETS 300 421 and ETS 300 429 standards compliant Reed Solomon[...]
More Than 650 European Universities and Research Institutions Invited to Develop Innovative Processor Designs Based on Sun Microsystems's OpenSPARC Technology[...]
Meridian FPGA is specifically designed to work with Altera Corporations latest release of its Quartuss® II software, version 8.1, to verify Clock Domain Crossings (CDC).[...]
The high-yield process features an Aluminum Copper (AlCu) backend metal scheme and is designed to meet energy reduction targets, while responding to the markets demand for smaller line width options[...]
Recognizing that many fabless chip startups are looking to avoid the cost of developing their own system-on-chip, but wish to create value in design, Xilinx is considering allowing such companies use [...]
Enabling worldwide operation, Staccatos 65nm all-CMOS implementation is the first single-chip solution to earn PHY certification for WiMedia Spectrum Extension Release (SER) in Band Groups 1, 3 and [...]
The report findings confirm the observation that venture capitalists are investing less in fabless and IDM companies because of higher design costs and consolidation, with the number and value of fabl[...]
The co-operation enables IC designs and IP to be ported to a manufacturing standard in just a few weeks, typically offering upto 10X reductions in cycle time and engineering costs as well as freeing u[...]
For fiscal 2008, total revenues were $59.3 million compared to $46.5 million for the prior year. Revenues for the fourth quarter of fiscal 2008 were $15.5 million, compared with $13.1 million for the [...]
CPRI v. 3.0 IP Core from Radiocomp[...]